TOF用タイムデジタルコンバーター
Kore Technology社製「4GHz Time-to-Digital Converter（TDC）」
仕 様
| 4GHz Time-to-Digital Converter (TDC) | |
| Timing resolution | 0.25ns |
| Number of hits per cycle | Unlimited |
| Maximum burst count rate | 2 GHz |
| Full speed front end FIFO depth | 8192 frames of 4ns |
| Maximum sustained count rate | > 17,000,000 counts/s (Theoretical) > 4,000,000 counts/s (Measured (※1)) |
| Maximum time stamp value | 0xFFFEFF ~4.2 millisec |
| Triggering modes | Fixed frequency free-running OR External Start trigger |
| Max cycle repetition rate | ≥ 1MHz (hardware) 200 kHz (current software limit) |
| Min cycle repetition rate (free running) | ≤ 20 Hz (hardware) 500 Hz (current software limit) |
| Min cycle repetition rate (External start trigger) | Unlimited |
| Number of cycles per experiment (on board counter) | 1 to 4×109 |
| Cycle counter reset time | < 1μs |
| Dead time between cycles | 36ns at cycle start and 4ns at end |
| Timing precision | < 470ps (1 hour measurement of peak at 500μs) estimated as 280ps internal trigger & 380 ps external trigger (※2) ) |
| Start/Stop input range | -5V to +5V (※3) |
| Start/Stop input threshold range | -2.5V to +2.5V (positive or negative timing edges selectable in software) |
| Start/Stop input termination (jumper selectable) | 50Ohm to ground (Normal) OR 50Ohm to -2V (ECL) |
| PC interface | USB 2.0 |
| Power requirement (typical for board) | +5V 730mA and -5.2V 65mA |
| Bench-top case dimensions | 280 x 300 x 70 mm |
| Bench-top power requirement | 230/115 VAC 50/60Hz 7watt |
| Software requirement | Windows XP or later |
※1 : Using the standard motherboard-based USB interface on an inexpensive general purpose PC purchased early 2009 [Pentium E5300 Dual Core 2.6 GHz with 1G RAM running WinXP svpk3. Device manager reports hub as “Intel 82801G (ICH7 Family) USB2 Enhanced Host Controller – 27CC”]
※2 : A measurement was made of the pulse width from a digital oscilloscope ‘Cal’ output, presumably crystal controlled, but no specification was available for pulse-width jitter. The TDC was triggered on each cycle by the leading edge of the pulse and the trailing edge was interpreted as a stop value. The histogram from a 1 hour measurement was fitted with a Gaussian curve, which had a full width half maximum of 470 ps. The leading edge will be subject to 250 ps of jitter because the ‘scope is not synchronised to the TDC. This element of the jitter would be absent in an experiment using internal cycle trigger. For estimation purposes it was assumed that the ‘scope and intrinsic TDC jitter were of similar size (both crystal controlled clocks) and that the various elements combined in quadrature (sum equals square-root of sum of squares).
※3 : The input comparator has protection diodes that limit the differential input voltage. This means as the difference between the input and the threshold exceeds about 1.25V a little more current will be drawn. This causes no damage but may give rise to double pulsing under some circumstances.